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<title>Using as: AArch64 Directives</title>

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<a name="AArch64-Directives"></a>
<div class="header">
<p>
Next: <a href="AArch64-Opcodes.html#AArch64-Opcodes" accesskey="n" rel="next">AArch64 Opcodes</a>, Previous: <a href="AArch64-Floating-Point.html#AArch64-Floating-Point" accesskey="p" rel="prev">AArch64 Floating Point</a>, Up: <a href="AArch64_002dDependent.html#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="AArch64-Machine-Directives"></a>
<h4 class="subsection">9.1.5 AArch64 Machine Directives</h4>

<a name="index-machine-directives_002c-AArch64"></a>
<a name="index-AArch64-machine-directives"></a>
<dl compact="compact">
<dd>

<a name="index-_002earch-directive_002c-AArch64"></a>
</dd>
<dt><code>.arch <var>name</var></code></dt>
<dd><p>Select the target architecture.  Valid values for <var>name</var> are the same as
for the <samp>-march</samp> commandline option.
</p>
<p>Specifying <code>.arch</code> clears any previously selected architecture
extensions.
</p>
<a name="index-_002earch_005fextension-directive_002c-AArch64"></a>
</dd>
<dt><code>.arch_extension <var>name</var></code></dt>
<dd><p>Add or remove an architecture extension to the target architecture.  Valid
values for <var>name</var> are the same as those accepted as architectural
extensions by the <samp>-mcpu</samp> commandline option.
</p>
<p><code>.arch_extension</code> may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
</p>

<a name="index-_002ebss-directive_002c-AArch64"></a>
</dd>
<dt><code>.bss</code></dt>
<dd><p>This directive switches to the <code>.bss</code> section.
</p>

<a name="index-_002ecpu-directive_002c-AArch64"></a>
</dd>
<dt><code>.cpu <var>name</var></code></dt>
<dd><p>Set the target processor.  Valid values for <var>name</var> are the same as
those accepted by the <samp>-mcpu=</samp> command line option.
</p>

<a name="index-_002edword-directive_002c-AArch64"></a>
</dd>
<dt><code>.dword <var>expressions</var></code></dt>
<dd><p>The <code>.dword</code> directive produces 64 bit values.
</p>

<a name="index-_002eeven-directive_002c-AArch64"></a>
</dd>
<dt><code>.even</code></dt>
<dd><p>The <code>.even</code> directive aligns the output on the next even byte
boundary.
</p>

<a name="index-_002einst-directive_002c-AArch64"></a>
</dd>
<dt><code>.inst <var>expressions</var></code></dt>
<dd><p>Inserts the expressions into the output as if they were instructions,
rather than data.
</p>

<a name="index-_002eltorg-directive_002c-AArch64"></a>
</dd>
<dt><code>.ltorg</code></dt>
<dd><p>This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
GAS maintains a separate literal pool for each section and each
sub-section.  The <code>.ltorg</code> directive will only affect the literal
pool of the current section and sub-section.  At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
</p>
<p>Note - older versions of GAS would dump the current literal
pool any time a section change occurred.  This is no longer done, since
it prevents accurate control of the placement of literal pools.
</p>



<a name="index-_002epool-directive_002c-AArch64"></a>
</dd>
<dt><code>.pool</code></dt>
<dd><p>This is a synonym for .ltorg.
</p>

<a name="index-_002ereq-directive_002c-AArch64"></a>
</dd>
<dt><code><var>name</var> .req <var>register name</var></code></dt>
<dd><p>This creates an alias for <var>register name</var> called <var>name</var>.  For
example:
</p>
<div class="smallexample">
<pre class="smallexample">        foo .req w0
</pre></div>



<a name="index-_002etlsdescadd-directive_002c-AArch64"></a>
</dd>
<dt><code><code>.tlsdescadd</code></code></dt>
<dd><p>Emits a TLSDESC_ADD reloc on the next instruction.
</p>
<a name="index-_002etlsdesccall-directive_002c-AArch64"></a>
</dd>
<dt><code><code>.tlsdesccall</code></code></dt>
<dd><p>Emits a TLSDESC_CALL reloc on the next instruction.
</p>
<a name="index-_002etlsdescldr-directive_002c-AArch64"></a>
</dd>
<dt><code><code>.tlsdescldr</code></code></dt>
<dd><p>Emits a TLSDESC_LDR reloc on the next instruction.
</p>

<a name="index-_002eunreq-directive_002c-AArch64"></a>
</dd>
<dt><code>.unreq <var>alias-name</var></code></dt>
<dd><p>This undefines a register alias which was previously defined using the
<code>req</code> directive.  For example:
</p>
<div class="smallexample">
<pre class="smallexample">        foo .req w0
        .unreq foo
</pre></div>

<p>An error occurs if the name is undefined.  Note - this pseudo op can
be used to delete builtin in register name aliases (eg &rsquo;w0&rsquo;).  This
should only be done if it is really necessary.
</p>


<a name="index-_002exword-directive_002c-AArch64"></a>
</dd>
<dt><code>.xword <var>expressions</var></code></dt>
<dd><p>The <code>.xword</code> directive produces 64 bit values.  This is the same
as the <code>.dword</code> directive.
</p>

</dd>
</dl>

<hr>
<div class="header">
<p>
Next: <a href="AArch64-Opcodes.html#AArch64-Opcodes" accesskey="n" rel="next">AArch64 Opcodes</a>, Previous: <a href="AArch64-Floating-Point.html#AArch64-Floating-Point" accesskey="p" rel="prev">AArch64 Floating Point</a>, Up: <a href="AArch64_002dDependent.html#AArch64_002dDependent" accesskey="u" rel="up">AArch64-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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